1. Technical Field
The present disclosure is related to a shift register circuit, and more particularly, to a shift register circuit having high driving ability.
2. Description of the Prior Art
Please refer to FIG. 1, which is diagram illustrating a prior art liquid crystal display (LCD) 100 having a shift register 102 and a pixel array 104. The shift register 102 includes a plurality of shift register circuits 106 for providing a plurality of gate signals transmitted to the pixel array 104 through a plurality of gate lines 108 in order to scan pixels in the pixel array 104. As the size of LCDs increases with time, the resolution of LCDs, that is, the number of pixels also increases, thereby increasing the number of gate lines 108 required to scan the pixel array 104. In order to scan more and more pixels at a limited frame rate, for example 60 Hz, the scanning speed of each gate line 108 must increase within a frame period, in other words, the scanning time of each gate line 108 must be reduced so as to scan all pixels completely within the frame period. However, with the reduction of the scanning time, the charging rate of pixels may decrease to a level which may result in poorer display quality.
Although a method for boosting voltage levels of the gate signals to alleviate the problem as set forth has been provided, the method may increase the dynamic power consumption and the static power consumption of the shift register circuits 106, thereby requiring bigger size transistors to be used in the shift register circuits 106 that occupy more layout area in the LCD, which contradicts the goal of minimizing layout area of the shift register circuits 106.